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1 isplsi ? and plsi ? 1032e high-density programmable logic functional block diagram features ? high density programmable logic 6000 pld gates 64 i/o pins, eight dedicated inputs 192 registers high speed global interconnect wide input gating for fast counters, state machines, address decoders, etc. small logic block size for random logic ? high performance e 2 cmos ? technology f max = 125 mhz maximum operating frequency t pd = 7.5 ns propagation delay ttl compatible inputs and outputs electrically erasable and reprogrammable non-volatile 100% tested at time of manufacture unused product term shutdown saves power ? isplsi offers the following added features in-system programmable (isp?) 5-volt only increased manufacturing yields, reduced time-to- market and improved product quality reprogram soldered devices for faster prototyping ? offers the ease of use and fast system speed of plds with the density and flexibility of field programmable gate arrays complete programmable device can combine glue logic and structured designs enhanced pin locking capability four dedicated clock input pins synchronous and asynchronous clocks programmable output slew rate control to minimize switching noise flexible pin placement optimized global routing pool provides global interconnectivity ? ispexpert? C logic compiler and complete isp device design systems from hdl synthesis through in-system programming superior quality of results tightly integrated with leading cae vendor tools productivity enhancing timing analyzer, explore tools, timing simulator and ispanalyzer? pc and unix platforms output routing pool output routing pool d7 d6 d5 d4 d3 d2 d1 d0 b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7 c7 c6 c5 c4 c3 c2 c1 c0 output routing pool output routing pool clk global routing pool (grp) 0139a(a1)-isp logic array dq dq dq dq glb description the isplsi and plsi 1032e are high density program- mable logic devices containing 192 registers, 64 universal i/o pins, eight dedicated input pins, four dedi- cated clock input pins and a global routing pool (grp). the grp provides complete interconnectivity between all of these elements. the isplsi 1032e features 5-volt in-system programmability and in-system diagnostic ca- pabilities. the isplsi 1032e device offers non-volatile reprogrammability of the logic, as well as the intercon- nects to provide truly reconfigurable systems. it is architecturally and parametrically compatible to the plsi 1032e device, but multiplexes four input pins to control in-system programming. a functional superset of the isplsi and plsi 1032 architecture, the isplsi and plsi 1032e devices add two new global output enable pins. the basic unit of logic on the isplsi and plsi 1032e devices is the generic logic block (glb). the glbs are labeled a0, a1d7 (see figure 1). there are a total of 32 glbs in the isplsi and plsi 1032e devices. each glb has 18 inputs, a programmable and/or/exclusive or array, and four outputs which can be configured to be either combinatorial or registered. inputs to the glb come from the grp and dedicated inputs. all of the glb outputs are brought back into the grp so that they can be connected to the inputs of any glb on the device. 1032e_06 copyright ? 1998 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. october 1998 tel. (503) 681-0118; 1-800-lattice; fax (503) 681-3037; http://www.latticesemi.com datasheet.in
2 specifications isplsi and plsi 1032e functional block diagram figure 1. isplsi and plsi 1032e functional block diagram the devices also have 64 i/o cells, each of which is directly connected to an i/o pin. each i/o cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional i/o pin with 3-state control. the signal levels are ttl compatible voltages and the output drivers can source 4 ma or sink 8 ma. each output can be programmed independently for fast or slow output slew rate to mini- mize overall output switching noise. eight glbs, 16 i/o cells, two dedicated inputs and one orp are connected together to make a megablock (see figure 1). the outputs of the eight glbs are connected to a set of 16 universal i/o cells by the orp. each isplsi and plsi 1032e device contains four megablocks. the grp has, as its inputs, the outputs from all of the glbs and all of the inputs from the bi-directional i/o cells. all of these signals are made available to the inputs of the glbs. delays through the grp have been equalized to minimize timing skew. clocks in the isplsi and plsi 1032e devices are se- lected using the clock distribution network. four dedicated clock pins (y0, y1, y2 and y3) are brought into the distribution network, and five clock outputs (clk 0, clk 1, clk 2, ioclk 0 and ioclk 1) are provided to route clocks to the glbs and i/o cells. the clock distri- bution network can also be driven from a special clock glb (c0 on the isplsi and plsi 1032e devices). the logic of this glb allows the user to create an internal clock from a combination of internal signals within the device. i/o 63 i/o 62 i/o 61 i/o 60 reset global routing pool (grp) clk 0 clk 1 clk 2 ioclk 0 ioclk 1 clock distribution network c7 c6 c5 c4 c3 c2 c1 c0 a0 a1 a2 a3 a4 a5 a6 a7 generic logic blocks (glbs) megablock output routing pool (orp) output routing pool (orp) output routing pool (orp) output routing pool (orp) input bus input bus *ispen/nc lnput bus lnput bus *isp control functions for isplsi 1032e only i/o 59 i/o 58 i/o 57 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 in 7 in 6 d7 d6 d5 d4 d3 d2 d1 d0 i/o 16 i/o 17 i/o 18 i/o 19 *sdo/in 2 *sclk/in 3 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 35 i/o 34 i/o 33 i/o 32 i/o 0 i/o 1 i/o 2 i/o 3 i/o 12 i/o 13 i/o 14 i/o 15 *sdi/in 0 *mode/in 1 i/o 8 i/o 9 i/o 10 i/o 11 i/o 4 i/o 5 i/o 6 i/o 7 i/o 47 i/o 46 i/o 45 i/o 44 goe 1/in 5 goe 0/in 4 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 i/o 38 i/o 37 i/o 36 y0 y1 y2 y3 b0 b1 b2 b3 b4 b5 b6 b7 datasheet.in
3 specifications isplsi and plsi 1032e absolute maximum ratings 1 supply voltage v cc .................................. -0.5 to +7.0v input voltage applied ........................ -2.5 to v cc +1.0v off-state output voltage applied ..... -2.5 to v cc +1.0v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). dc recommended operating conditions t a = 0 c to + 70 c t a = -40 c to + 85 c symbol table 2-0005/1032e v cc v ih v il parameter supply voltage input high voltage input low voltage min. max. units 4.75 4.5 2.0 0 5.25 5.5 v cc +1 0.8 v v v v commercial industrial capacitance (t a =25 o c, f=1.0 mhz) data retention specifications table 2-0008/1032e parameter plsi erase/reprogram cycles 100 data retention minimum maximum units isplsi erase/reprogram cycles 20 10000 cycles years cycles c symbol table 2-0006/1032e c parameter y0 clock capacitance 15 units typical test conditions 1 2 8 dedicated input, i/o, y1, y2, y3, clock capacitance (commercial/industrial) pf pf v = 5.0v, v = 2.0v v = 5.0v, v = 2.0v cc cc pin pin datasheet.in
4 specifications isplsi and plsi 1032e output load conditions (see figure 2) switching test conditions test condition r1 r2 cl a 470 w 390 w 35pf b 390 w 35pf 470 w 390 w 35pf active high active low c 470 w 390 w 5pf 390 w 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2-0004/1032e figure 2. test load + 5v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213a dc electrical characteristics over recommended operating conditions v ol symbol 1. one output at a time for a maximum duration of one second. v = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2. measured using eight 16-bit counters. 3. typical values are at v = 5v and t = 25 c. 4. maximum i varies widely with specific device configuration and operating frequency. refer to the power consumption section of this data sheet and thermal management section of the lattice semiconductor data book or cd-rom to estimate maximum i . table 2-0007/1032e 1 v oh i ih i il i il-isp parameter i il-pu i os 2, 4 i cc output low voltage output high voltage input or i/o high leakage current input or i/o low leakage current ispen input low leakage current i/o active pull-up current output short circuit current operating power supply current i = 8 ma i = -4 ma 3.5v v v 0v v v (max.) 0v v v 0v v v v = 5v, v = 0.5v v = 0.5v, v = 3.0v f = 1 mhz ol oh in il in cc in il in il cc out clock il ih condition min. typ. max. units 3 2.4 190 190 0.4 10 -10 -150 -150 -200 v v m a m a m a m a ma ma ma cc a out cc cc commercial industrial input pulse levels table 2-0003/1032e input rise and fall time 10% to 90% input timing reference levels output timing reference levels output load gnd to 3.0v 1.5v 1.5v see figure 2 3-state levels are measured 0.5v from steady-state active level. -125 others 2 ns 3 ns datasheet.in
5 specifications isplsi and plsi 1032e t pd1 units test cond. 1. unless noted otherwise, all parameters use the grp, 20 ptxor path, orp and y0 clock. 2. refer to timing model in this data sheet for further details. 3. standard 16-bit counter using grp feedback. 4. reference switching test conditions section. table 2-0030a/1032e 1 4 3 1 tsu2 + tco1 ( ) -100 min. max. description # 2 parameter a 1 data propagation delay, 4pt bypass, orp bypass 10.0 ns t pd2 a 2 data propagation delay, worst case path ns f max (int.) a 3 clock frequency with internal feedback 100 mhz f max (ext.) 4 clock frequency with external feedback mhz f max (tog.) 5 clock frequency, max. toggle mhz t su1 6 glb reg. setup time before clock,4 pt bypass ns t co1 a 7 glb reg. clock to output delay, orp bypass ns t h1 8 glb reg. hold time after clock, 4 pt bypass ns t su2 9 glb reg. setup time before clock ns t co2 10 glb reg. clock to output delay ns t h2 11 glb reg. hold time after clock ns t r1 a 12 ext. reset pin to output delay ns t rw1 13 ext. reset pulse duration ns t ptoeen b 14 input to output enable ns t ptoedis c 15 input to output disable ns t wh 18 external synchronous clock pulse duration, high 4.0 ns t wl 19 external synchronous clock pulse duration, low 4.0 ns t su3 20 i/o reg. setup time before ext. sync clock (y2, y3) ns t h3 21 i/o reg. hold time after ext. sync. clock (y2, y3) ns 71.0 125 7.0 0.0 8.0 0.0 6.5 3.5 0.0 12.5 6.0 7.0 13.5 15.0 15.0 ( ) 1 twh + tw1 t goeen b 16 global oe output enable ns 9.0 t goedis c 17 global oe output disable ns 9.0 -125 min. max. 7.5 125 3.0 3.0 91.0 167 5.0 0.0 6.0 0.0 5.0 3.0 0.0 10.0 5.0 6.0 10.0 12.0 12.0 7.0 7.0 external timing parameters over recommended operating conditions datasheet.in
6 specifications isplsi and plsi 1032e use 1032e-100 for new designs t pd1 units test cond. 1. unless noted otherwise, all parameters use the grp, 20 ptxor path, orp and y0 clock. 2. refer to timing model in this data sheet for further details. 3. standard 16-bit counter using grp feedback. 4. reference switching test conditions section. table 2-0030b/1032e 1 4 3 1 tsu2 + tco1 ( ) -70 min. max. description # 2 parameter a 1 data propagation delay, 4pt bypass, orp bypass 15.0 ns t pd2 a 2 data propagation delay, worst case path ns f max (int.) a 3 clock frequency with internal feedback 70.0 mhz f max (ext.) 4 clock frequency with external feedback mhz f max (tog.) 5 clock frequency, max. toggle mhz t su1 6 glb reg. setup time before clock,4 pt bypass ns t co1 a 7 glb reg. clock to output delay, orp bypass ns t h1 8 glb reg. hold time after clock, 4 pt bypass ns t su2 9 glb reg. setup time before clock ns t co2 10 glb reg. clock to output delay ns t h2 11 glb reg. hold time after clock ns t r1 a 12 ext. reset pin to output delay ns t rw1 13 ext. reset pulse duration ns t ptoeen b 14 input to output enable ns t ptoedis c 15 input to output disable ns t wh 18 external synchronous clock pulse duration, high 5.0 ns t wl 19 external synchronous clock pulse duration, low 5.0 ns t su3 20 i/o reg. setup time before ext. sync clock (y2, y3) ns t h3 21 i/o reg. hold time after ext. sync. clock (y2, y3) ns 56.0 100 9.0 0.0 11.0 0.0 10.0 4.0 0.0 17.5 7.0 8.0 15.0 18.0 18.0 ( ) 1 twh + tw1 t goeen b 16 global oe output enable ns 12.0 t goedis c 17 global oe output disable ns -90 min. max. 10.0 90.0 0.0 8.5 0.0 6.5 4.0 4.0 3.5 0.0 69.0 125 7.5 6.0 7.0 13.5 15.0 15.0 12.5 9.0 9.0 12.0 -80 min. max. 12.0 80.0 4.5 4.5 61.0 111 8.5 0.0 10.0 0.0 8.0 3.5 0.0 15.0 6.5 7.5 14.0 16.5 16.5 10.0 10.0 external timing parameters over recommended operating conditions datasheet.in
7 specifications isplsi and plsi 1032e grp delay, 32 glb loads t iobp 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036a/1032e inputs units -100 min. min. max. max. description # 2 param. 22 i/o register bypass ns t iolat 23 i/o latch delay ns t grp32 33 ns glb t 1ptxor 36 1 prod.term/xor path delay ns t 20ptxor 37 20 prod. term/xor path delay ns t xoradj 38 xor adjacent path delay ns t gbp 39 glb register bypass delay ns t gsu 40 glb register setup time before clock ns t gh 41 glb register hold time after clock ns t gco 42 glb register clock to output delay ns 3 t gro 43 glb register reset to output delay ns t ptre 44 glb prod.term reset to register delay ns t ptoe 45 glb prod. term output enable to i/o cell delay ns t ptck 46 glb prod. term clock delay ns orp grp t 4ptbpc 34 4 prod.term bypass path delay (combinatorial) ns t 4ptbpr 35 4 prod. term bypass path delay (registered) ns t orp 47 orp delay ns t orpbp 48 orp bypass delay ns t iosu 24 i/o register setup time before clock ns t ioh 25 i/o register hold time after clock ns t ioco 26 i/o register clock to out delay ns t ior 27 i/o register reset to out delay ns t din 28 dedicated input delay ns t grp16 32 grp delay, 16 glb loads ns t grp8 31 grp delay, 8 glb loads ns t grp4 30 grp delay, 4 glb loads ns t grp1 29 grp delay, 1 glb load ns 0.0 -125 0.1 4.5 2.9 3.0 0.0 0.3 1.9 3.8 3.6 5.0 5.0 0.4 2.3 4.9 3.9 5.4 3.9 4.0 4.0 1.0 0.0 4.6 4.6 2.3 2.8 2.3 2.0 1.8 0.5 5.8 3.5 3.5 0.0 0.3 2.3 4.2 4.6 5.8 6.3 1.0 2.5 6.2 4.5 7.2 5.3 5.3 4.7 1.0 5.0 5.0 2.7 3.0 2.4 2.4 1.9 internal timing parameters 1 datasheet.in
8 specifications isplsi and plsi 1032e internal timing parameters 1 use 1032e-100 for new designs grp delay, 32 glb loads t iobp 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036b/1032e inputs units -80 min. -70 min. max. max. description # 2 param. 22 i/o register bypass ns t iolat 23 i/o latch delay ns t grp32 33 ?s glb t 1ptxor 36 1 prod.term/xor path delay ns t 20ptxor 37 20 prod. term/xor path delay ns t xoradj 38 xor adjacent path delay ns t gbp 39 glb register bypass delay ?s t gsu 40 glb register setup time before clock ns t gh 41 glb register hold time after clock ns t gco 42 glb register clock to output delay ns 3 t gro 43 glb register reset to output delay ns t ptre 44 glb prod.term reset to register delay ns t ptoe 45 glb prod. term output enable to i/o cell delay ns t ptck 46 glb prod. term clock delay ns orp grp min. max. t 4ptbpc 34 4 prod.term bypass path delay (combinatorial) ns t 4ptbpr 35 4 prod. term bypass path delay (registered) ns 0.5 7.9 4.5 t orp 47 orp delay ns t orpbp 48 orp bypass delay 0.0 ns t iosu 24 i/o register setup time before clock 3.5 ns t ioh 25 i/o register hold time after clock 0.0 ns t ioco 26 i/o register clock to out delay ns t ior 27 i/o register reset to out delay ns t din 28 dedicated input delay ns t grp16 32 grp delay, 16 glb loads ns t grp8 31 grp delay, 8 glb loads ns t grp4 30 grp delay, 4 glb loads ns t grp1 29 grp delay, 1 glb load ns 0.3 2.7 4.8 6.6 7.8 8.2 1.3 2.9 6.4 5.5 8.0 7.1 6.7 5.8 1.0 0.0 5.4 5.4 2.8 3.5 2.8 2.5 2.2 0.5 8.8 4.8 4.0 0.0 0.3 3.3 5.6 8.3 8.7 9.2 1.6 2.9 6.8 5.8 9.0 8.8 7.2 6.2 1.0 6.1 6.0 2.8 4.0 3.2 2.5 2.5 -90 0.2 6.8 4.1 3.5 0.0 0.3 2.3 4.4 5.6 6.8 7.1 0.4 2.9 6.3 5.1 7.1 5.7 6.1 5.3 1.0 0.0 5.0 5.0 2.6 3.2 2.6 2.3 2.1 datasheet.in
9 specifications isplsi and plsi 1032e internal timing parameters 1 t ob 1. internal timing parameters are not tested and are for reference only. table 2-0037a/1032e outputs units -100 min. min. max. max. description # param. 49 output buffer delay ns t oen 51 i/o cell oe to output enabled ns t gy0 54 clk delay, y0 to global glb clk line (ref. clk) ns global reset clocks t gr 59 global reset to glb and i/o registers ns t odis 52 i/o cell oe to output disabled ns t gy1/2 55 clk delay, y1 or y2 to global glb clk line ns t gcp 56 clk delay, clock glb to global glb clk line ns t ioy2/3 57 clk delay, y2 or y3 to i/o cell global clk line ns t iocp 58 clk delay, clk glb to i/o cell global clk line ns t goe 53 global oe ns t sl 50 output buffer delay, slew limited adder ns -125 1.5 1.5 0.8 0.0 0.8 2.0 5.1 1.5 4.3 5.1 1.5 1.8 0.0 1.8 3.9 10.0 1.4 1.4 0.8 0.0 0.8 1.3 4.3 1.4 2.8 4.3 1.4 1.8 0.0 1.8 2.7 9.9 datasheet.in
10 specifications isplsi and plsi 1032e use 1032e-100 for new designs internal timing parameters 1 t ob 1. internal timing parameters are not tested and are for reference only. table 2-0037b/1032e outputs units -80 min. -70 min. max. max. description # param. 49 output buffer delay ns t oen 51 i/o cell oe to output enabled ns t gy0 54 clock delay, y0 to global glb clock line (ref. clock) 1.5 ns global reset clocks t gr 59 global reset to glb and i/o registers ns t odis 52 i/o cell oe to output disabled ns t gy1/2 55 clock delay, y1 or y2 to global glb clock line 2.6 ns t gcp 56 clock delay, clock glb to global glb clock line 0.8 ns t ioy2/3 57 clock delay, y2 or y3 to i/o cell global clock line 0.0 ns t iocp 58 clock delay, clock glb to i/o cell global clock line 0.8 ns t goe 53 global oe ns min. max. t sl 50 output buffer delay, slew limited adder ns 2.1 5.7 1.5 4.5 5.7 3.1 1.8 0.0 1.8 4.3 10.0 1.5 1.5 0.8 0.0 0.8 2.6 6.2 1.5 4.6 6.2 1.5 1.8 0.0 1.8 5.8 10.0 -90 1.4 2.4 0.8 0.0 0.8 1.7 5.3 1.4 4.5 5.3 2.9 1.8 0.0 1.8 3.7 10.0 datasheet.in
11 specifications isplsi and plsi 1032e isplsi and plsi 1032e timing model glb reg delay i/o pin (output) orp delay 0491 feedback reg 4 pt bypass 20 pt xor delays control pts input register clock distribution i/o pin (input) y0 y1,2,3 d q grp4 glb reg bypass orp bypass dq rst re oe ck i/o reg bypass i/o cell orp glb grp i/o cell #23 - 27 #30 #35 #34 comb 4 pt bypass #36 - 38 #55 - 58 #44 - 46 #54 #53 #47 #48 reset ded. in goe 0,1 #28 #22 rst #59 #59 #39 #40 - 43 #51, 52 #49, 50 grp loading delay #29, 31 - 33 derivations of t su, t h and t co from the product term clock 1 = = = = t su 2.2 ns logic + reg su - clock (min) ( t iobp + t grp4 + t 20ptxor) + ( t gsu) ?( t iobp + t grp4 + t ptck(min)) (#22 + #30 + #37) + (#40) ?(#22 + #30 + #46) (0.3 + 2.0 + 5.0) + (0.1) ?(0.3 + 2.0 + 2.9) = = = = t h clock (max) + reg h - logic ( t iobp + t grp4 + t ptck(max)) + ( t gh) ?( t iobp + t grp4 + t 20ptxor) (#22 + #30 + #46) + (#41) - (#22 + #30 + #37) (0.3 + 2.0 + 4.0) + (4.5) ?(0.3 + 2.0 + 5.0) = = = = t co clock (max) + reg co + output ( t iobp + t grp4 + t ptck(max)) + ( t gco) + ( t orp + t ob) (#22 + #30 + #46) + (#42) + (#47 + #49) (0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3) table 2-0042a/1032e derivations of t su, t h and t co from the clock glb 1 = = = = t su logic + reg su - clock (min) ( t iobp + t grp4 + t 20ptxor) + ( t gsu) ?( t gy0(min) + t gco + t gcp(min)) (#22 + #30 + #37) + (#40) ?(#54 + #42 + #56) (0.3 + 2.0 + 5.0) + (0.1) ?(1.4 + 2.3 + 0.8) = = = = t h clock (max) + reg h - logic ( t gy0(max) + t gco + t gcp(max)) + ( t gh) ?( t iobp + t grp4 + t 20ptxor) (#54 + #42 + #56) + (#41) ?(#22 + #30 + #37) (1.4 + 2.3 + 1.8) + (4.5) ?(0.3 + 2.0 + 5.0) = = = = t co clock (max) + reg co + output ( t gy0(max) + t gco + t gcp(max)) + ( t gco) + ( t orp + t ob) (#54 + #42 + #56) + (#42) + (#47 + #49) (1.4 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3) 3.5 ns 10.9 ns 2.9 ns 2.7 ns 5.5 ns 1. calculations are based upon timing specifications for the isplsi and plsi 1032e-125. datasheet.in
12 specifications isplsi and plsi 1032e maximum grp delay vs glb loads glb load 3.0 5.0 1 8 16 32 grp delay (ns) 4.0 4 2.0 6.0 grp/glb/1032e isplsi and plsi 1032e-70 isplsi and plsi 1032e-90/100 isplsi and plsi 1032e-80 isplsi and plsi 1032e-125 1.0 power consumption figure 3. typical device power consumption vs fmax power consumption in the isplsi and plsi 1032e device depends on two primary factors: the speed at which the device is operating, and the number of product terms used. figure 3 shows the relationship between power and operating speed. 0127/1032e f max (mhz) notes: configuration of eight 16-bit counters typical current at 5v, 25 c 100 200 300 0 20 40 60 80 100 i cc (ma) isplsi and plsi 1032e 250 150 350 125 150 cc i can be estimated for the isplsi and plsi 1032e using the following equation: i (ma) = 15 + (# of pts * 0.59) + (# of nets * max freq * 0.0078) where: # of pts = number of product terms used in design # of nets = number of signals used in device max freq = highest clock frequency to the device (in mhz) the i estimate is based on typical conditions (v cc = 5.0v, room temperature) and an assumption of four glb loads on average exists. these values are for estimates only. since the value of i is sensitive to operating conditions and the program in the device, the actual i should be verified. cc cc cc cc datasheet.in
13 specifications isplsi and plsi 1032e pin description input - this pin performs two functions. when ispen is logic low, it functions as pin to control the operation of the isp state machine. it is a dedicated input pin when ispen is logic high. this is a dual function pin. it can be used either as global output enable for all i/o cells or it can be used as a dedicated input pin. this is a dual function pin. it can be used either as global output enable for all i/o cells or it can be used as a dedicated input pin. dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any glb on the device. dedicated clock input. this clock input is connected to one of the clock inputs of all of the glbs on the device. input/output pins - these are the general purpose i/o pins used by the logic array. name table 2-0002a/1032e plcc pin numbers description 26, 30, 34, 38, 45, 49, 53, 57, 68, 72, 76, 80, 3, 7, 11, 15, 27, 31, 35, 39, 46, 50, 54, 58, 69, 73, 77, 81, 4, 8, 12, 16, 28, 32, 36, 40, 47, 51, 55, 59, 70, 74, 78, 82, 5, 9, 13, 17, i/o 0 - i/o 3 i/o 4 - i/o 7 i/o 8 - i/o 11 i/o 12 - i/o 15 i/o 16 - i/o 19 i/o 20 - i/o 23 i/o 24 - i/o 27 i/o 28 - i/o 31 i/o 32 - i/o 35 i/o 36 - i/o 39 i/o 40 - i/o 43 i/o 44 - i/o 47 i/o 48 - i/o 51 i/o 52 - i/o 55 i/o 56 - i/o 59 i/o 60 - i/o 63 29, 33, 37, 41, 48, 52, 56, 60, 71, 75, 79, 83, 6, 10, 14, 18 66 y1 20 y0 42 mode/in 1 2 ground (gnd) gnd vcc vcc 21, 65 nc 1 goe 0/in 4 3 dedicated input pins to the device. in 6, in 7 goe 1/in 5 3 2, 84 67 19 input - dedicated in-system programming enable input pin. this pin is brought low to enable the programming mode. the mode, sdi, sdo and sclk options become active. 23 ispen/nc 1,2 input - this pin performs two functions. when ispen is logic low, it functions as an input pin to load programming data into the device. sdi/in 0 is also used as one of the two control pins for the isp state machine. it is a dedicated input pin when ispen is logic high. 25 sdi/in 0 2 44 sdo/in 2 2 output/input - this pin performs two functions. when ispen is logic low, it functions as an output pin to read serial shift register data. it is a dedicated input pin when ispen is logic high. 61 sclk/in 3 2 input - this pin performs two functions. when ispen is logic low, it functions as a clock pin for the serial shift register. it is a dedicated input pin when ispen is logic high. active low (0) reset pin which resets all of the glb and i/o registers in the device. 24 reset dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any glb and/or any i/o cell on the device. 63 y2 dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any i/o cell on the device. 62 y3 1, 22, 43, 64 12, 1, 26, 51, 76, 64 2, 24, 25, no connect. 27, 49, 50, 52, 74, 75, 77, 99, 100 1. nc pins are not to be connected to any ative signals, vcc or gnd. 2. pins have dual function capability for isplsi 1032e only. 3. pins have dual function capability which is software selectable. tqfp pin numbers 17, 21, 29, 33, 40, 44, 48, 56, 67, 71, 79, 83, 90, 94, 98, 6, 18, 22, 30, 34, 41, 45, 53, 57, 68, 72, 80, 84, 91, 95, 3, 7, 19, 23, 31, 35, 42, 46, 54, 58, 69, 73, 81, 85, 92, 96, 4, 8, 20, 28, 32, 36, 43, 47, 55, 59, 70, 78, 82, 86, 93, 97, 5, 9 65 11 37 89, 87 66 10 14 16 39 60 15 62 61 13, 38, 63, 88 datasheet.in
14 specifications isplsi and plsi 1032e isplsi and plsi 1032e 84-pin plcc pinout diagram i/o 38 i/o 37 i/o 36 i/o 35 i/o 34 i/o 33 i/o 32 goe 0/in 4 3 y1 vcc gnd y2 y3 sclk/in 3 2 i/o 31 i/o 30 i/o 29 i/o 28 i/o 27 i/o 26 i/o 25 i/o 57 i/o 58 i/o 59 i/o 60 i/o 61 i/o 62 i/o 63 in 7 y0 vcc gnd 1,2 ispen /nc reset 2 sdi/in 0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 in 6 gnd goe 1/in 5 3 i/o 47 i/o 46 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 2 mode/in 1 gnd 2 sdo/in 2 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 isplsi 1032e plsi 1032e top view 0123-32-isp 1. nc pins are not to be connected to any active signals, vcc or gnd. 2. pins have dual function capability for isplsi 1032e only (except pin 23, which is ispen only). 3. pins have dual function capability which is software selectable. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 111098765432184838281807978777675 pin configurations datasheet.in
15 specifications isplsi and plsi 1032e nc nc i/o 57 i/o 58 i/o 59 i/o 60 i/o 61 i/o 62 i/o 63 in 7 y0 vcc gnd ispen reset 1 sdi/in 0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 nc nc nc nc i/o 38 i/o 37 i/o 36 i/o 35 i/o 34 i/o 33 i/o 32 goe 0/in 4 2 y1 vcc gnd y2 y3 sclk/in 3 1 i/o 31 i/o 30 i/o 29 i/o 28 i/o 27 i/o 26 i/o 25 nc nc nc nc i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 in 6 gnd goe 1/in 5 2 i/o 47 i/o 46 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 nc nc nc nc i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 1 mode/in1 gnd 1 sdo/in 2 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 58 isplsi 1032e top view 1. pins have dual function capability. 2. pins have dual function capability which is software selectable. 0766a-32e-isp isplsi 1032e 100-pin tqfp pinout diagram pin configurations datasheet.in
16 specifications isplsi and plsi 1032e note: use isplsi for all new designs. part number description device number grade blank = commercial i = industrial 1032e xxx x x x speed 125 = 125 mhz f max 100 = 100 mhz f max 90 = 90 mhz f max 80 = 80 mhz f max 70 = 70 mhz f max power l = low package j = plcc t = tqfp device family 0212/1032e (is)plsi isplsi and plsi 1032e ordering information 100 100 84-pin plcc 10 10 isplsi 1032e-100lj 100-pin tqfp isplsi 1032e-100lt plsi table 2-0041a/1032e 90 90 84-pin plcc 10 10 isplsi 1032e-90lj* 100-pin tqfp isplsi 1032e-90lt* 80 12 84-pin plcc isplsi 1032e-80lj* family f max (mhz) 125 ordering number package t pd (ns) 7.5 isplsi 84-pin plcc isplsi 1032e-125lj 80 70 70 100-pin tqfp 84-pin plcc 12 15 15 isplsi 1032e-80lt* isplsi 1032e-70lj 100-pin tqfp isplsi 1032e-70lt 125 100-pin tqfp 7.5 isplsi 1032e-125lt 80 70 84-pin plcc 12 15 plsi 1032e-80lj* 84-pin plcc plsi 1032e-70lj 125 100 84-pin plcc 7.5 10 plsi 1032e-125lj 84-pin plcc plsi 1032e-100lj 90 84-pin plcc 10 plsi 1032e-90lj* commercial *use isplsi 1032e-100 for all new designs. table 2-0041b/1032e family f max (mhz) 70 70 ordering number package 84-pin plcc 100-pin tqfp t pd (ns) 15 15 isplsi isplsi 1032e-70lji isplsi 1032e-70lti industrial datasheet.in

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